Instructions:
On the left, put the output of cadence. Should look like this:
// Library - ece555_project, Cell - ADDER_1bit, View - schematic
// LAST TIME SAVED: Dec 8 17:21:49 2009
// NETLIST TIME: Dec 10 13:37:11 2009
`timescale 1ns / 1ns
module ADDER_1BIT ( CO, S, A, B, CI, ADDER_EN );
output CO, S;
input A, B, CI, ADDER_EN;
specify
specparam CDS_LIBNAME = "ece555_project";
specparam CDS_CELLNAME = "ADDER_1bit";
specparam CDS_VIEWNAME = "schematic";
endspecify
nmos4 N21 ( GND_, ADDER_EN_N, ADDER_EN, cds_globals.GND_);
nmos4 N19 ( cds_globals.GND_, NET089, ADDER_EN, S);
nmos4 N18 ( cds_globals.GND_, CO, NET13, cds_globals.GND_);
nmos4 N17 ( cds_globals.GND_, NET089, NET043, cds_globals.GND_);
nmos4 N15 ( cds_globals.GND_, NET035, B, NET039);
nmos4 N13 ( cds_globals.GND_, NET039, A, cds_globals.GND_);
nmos4 N16 ( cds_globals.GND_, NET043, CI, NET035);
nmos4 N11 ( cds_globals.GND_, NET043, NET13, NET051);
nmos4 N10 ( cds_globals.GND_, NET051, CI, cds_globals.GND_);
nmos4 N9 ( cds_globals.GND_, NET051, A, cds_globals.GND_);
nmos4 N8 ( cds_globals.GND_, NET051, B, cds_globals.GND_);
nmos4 N7 ( cds_globals.GND_, NET13, A, NET5);
nmos4 N4 ( cds_globals.GND_, NET13, CI, NET17);
nmos4 N6 ( cds_globals.GND_, NET5, B, cds_globals.GND_);
nmos4 N1 ( cds_globals.GND_, NET17, A, cds_globals.GND_);
nmos4 N5 ( cds_globals.GND_, NET17, B, cds_globals.GND_);
pmos4 P18 ( cds_globals.VDD_, NET089, ADDER_EN_N, S);
pmos4 P19 ( cds_globals.VDD_, ADDER_EN_N, ADDER_EN, cds_globals.VDD_);
pmos4 P16 ( cds_globals.VDD_, CO, NET13, cds_globals.VDD_);
pmos4 P15 ( cds_globals.VDD_, NET089, NET043, cds_globals.VDD_);
pmos4 P14 ( cds_globals.VDD_, NET090, A, cds_globals.VDD_);
pmos4 P13 ( cds_globals.VDD_, NET094, B, NET090);
pmos4 P12 ( cds_globals.VDD_, NET043, CI, NET094);
pmos4 P11 ( cds_globals.VDD_, NET043, NET13, NET0107);
pmos4 P10 ( cds_globals.VDD_, NET0107, CI, cds_globals.VDD_);
pmos4 P9 ( cds_globals.VDD_, NET0107, B, cds_globals.VDD_);
pmos4 P8 ( cds_globals.VDD_, NET0107, A, cds_globals.VDD_);
pmos4 P6 ( cds_globals.VDD_, NET13, CI, NET37);
pmos4 P7 ( cds_globals.VDD_, NET13, A, NET24);
pmos4 P4 ( cds_globals.VDD_, NET37, B, cds_globals.VDD_);
pmos4 P5 ( cds_globals.VDD_, NET24, B, cds_globals.VDD_);
pmos4 P1 ( cds_globals.VDD_, NET37, A, cds_globals.VDD_);
endmodule
It will be converted to an output that works for ncverilog (rename nmos4 to nmos, move terminals around, rename gnds and vdds)
// Library - ece555_project, Cell - ADDER_1bit, View - schematic
// LAST TIME SAVED: Dec 8 17:21:49 2009
// NETLIST TIME: Dec 10 13:37:11 2009
`timescale 1ns / 1ns
module ADDER_1BIT ( CO, S, A, B, CI, ADDER_EN );
output CO, S;
input A, B, CI, ADDER_EN;
specify
specparam CDS_LIBNAME = "ece555_project";
specparam CDS_CELLNAME = "ADDER_1bit";
specparam CDS_VIEWNAME = "schematic";
endspecify
nmos N21 (ADDER_EN_N, 0, ADDER_EN);
nmos N19 (NET089, S, ADDER_EN);
nmos N18 (CO, 0, NET13);
nmos N17 (NET089, 0, NET043);
nmos N15 (NET035, NET039, B);
nmos N13 (NET039, 0, A);
nmos N16 (NET043, NET035, CI);
nmos N11 (NET043, NET051, NET13);
nmos N10 (NET051, 0, CI);
nmos N9 (NET051, 0, A);
nmos N8 (NET051, 0, B);
nmos N7 (NET13, NET5, A);
nmos N4 (NET13, NET17, CI);
nmos N6 (NET5, 0, B);
nmos N1 (NET17, 0, A);
nmos N5 (NET17, 0, B);
pmos P18 (NET089, S, ADDER_EN_N);
pmos P19 (ADDER_EN_N, 1, ADDER_EN);
pmos P16 (CO, 1, NET13);
pmos P15 (NET089, 1, NET043);
pmos P14 (NET090, 1, A);
pmos P13 (NET094, NET090, B);
pmos P12 (NET043, NET094, CI);
pmos P11 (NET043, NET0107, NET13);
pmos P10 (NET0107, 1, CI);
pmos P9 (NET0107, 1, B);
pmos P8 (NET0107, 1, A);
pmos P6 (NET13, NET37, CI);
pmos P7 (NET13, NET24, A);
pmos P4 (NET37, 1, B);
pmos P5 (NET24, 1, B);
pmos P1 (NET37, 1, A);
endmodule